RISC-V CPU IP Solution

900
Series 32-Bit & 64-Bit High Performance Processor
900 series processors include three products: N900 (32-bit), nx900 (64 bit) and ux900 (64 bit + MMU). With MMU, ux900 can run heavy operating systems, such as Linux. It is very suitable for replacing ARM cortex-m7, R7, R8, A35, A53, A55, which can be applied to AIoT edge computing, data center, network equipment, and other fields.
900 Core Complex
Debug
900 Core
VPU
MMU
NMI
ECLIC
Timer
WFI/WFE
NICE
FPU
DSP
MUL/DIV
900 uCore
ICache
DCache
TEE
PMP
ILM
DLM
AHB-Lite
AXI
  • Real-time Feature
  • RV32 IMACFDPB RV64 IMACFDPB
  • 9 Stage Pipeline Single-issue,Dual-issue
  • I/D Cache
  • Machine, User,Supervisor-Mode
  • Security(PMP,TEE)
  • NICE Extension
  • AXI system bus
  • RISC-V Standard Debug
  • JTAG & 2-wire JTAG
  • Low Latency Interrupt
  • Full Dev Kit & SDK
900-SMP(multi-core) is the configurable version of 900 series processor, which supports SMP (symmetric multiprocessing) mode.
Cluster Interrupt Module ECLIC/ PLIC
Cluster Debug Module JTAG/ cJTAG
core 0
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
NICE IF
ILM w/ECC
DLM w/ECC
core 1
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
NICE IF
ILM w/ECC
DLM w/ECC
core 2
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
NICE IF
ILM w/ECC
DLM w/ECC
core n
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
NICE IF
ILM w/ECC
DLM w/ECC
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Slave Port
Snoop Filte
Snoop Control Unit
IOCP
...
IOCP
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Cluster Cache
128KB-4MB
|
Configurable CLM
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Cluster Memory Ports
Cluster Peripheral Ports
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900 Series Single Core Features
  • RISC-V RV32/64IMACFDPBVK ISA supported
  • Dual Issue, in-order 9 stage Harvard Pipeline
  • 64-bit AXI system bus, configurable 32-bit AHB-Lite slave port
  • Double, Single and Half-Precision floating point
  • ConfigurableSIMD DSP Extension
  • Full Vector Extension with configurable VLEN & DLEN
  • Configurable Instruction and Data Memory
  • Configurable ILM (Instruction Local Memory) with ECC
  • Configurable DLM (Data Local Memory) with ECC
  • ConfigurableMMU supported(SV32/SV39/SV48)
  • PMP supported and TEE supported to meet the system security needs
  • Full Standard Debug Function with JTAG and cJTAG Port
  • Full Standard RISC-V Toolchain, and Linux\Windows IDE supported
900 series SMP Multi Core Features
  • Multi-core Dual-mode feature Processor and Application Processor model support
  • Up to 16 SMP cores in one Cluster
  • SoC Connectivity
    • Configurable Cluster Memory Ports(64/128/256/512 Bits)
    • Cluster peripheral ports supporting 32-bit AHB Lite protocol
  • IOCP (I/O Coherent Ports),Up to 16 Configured IO Coherency Ports supported
  • Support Hardware Data prefetching mechanism
  • Cluster Cache
    • Configurable Cluster Cache
    • Configurable Cache Line Size（64Bytes）
    • Configurable Tag RAM and Data RAM circle
    • Support to LOCK, FLUSH and/or INVAL cachelines
    • 16-way associative
    • ConfigurableCluster Local Memory
Common configurations and applications of the 900 series
N900 Core Machine/Supervisor/
User Mode
ILM
DLM
DSP/FPU
  • Series 32-Bit, in-order 9 stage Harvard Pipeline,Single-Issue or Dual-Issue
  • RISC-V RV32/64IMACFDPVBZfh ISA supported
  • On chip instruction and data SRAM configurable
  • SMP supports up to 16 cores
MCU
AIoT
Automotive Electronics
U900 Core Machine/Supervisor/
User Mode
ICache w/ECC
DCache w/ECC
FPU/VPU
MMU
  • Series 32-Bit, in-order 9 stage Harvard Pipeline,Single-Issue or Dual-Issue
  • RISC-V RV32/64IMACFDPVBZfh ISA supported
  • Configurable I-Cache & D-Cache with ECC, 16-64KB
  • MMU support,Support both 32b & 64b Linux Kernel
  • SMP supports up to 16 cores
32b Linux
Security
NX900 Core Machine/Supervisor/
User Mode
ILM
DLM
ICache w/ECC
DCache w/ECC
DSP/FPU/VPU
  • Series 64-Bit, in-order 9 stage Harvard Pipeline,Single-Issue or Dual-Issue
  • RISC-V RV32/64IMACFDPVBZfh ISA supported
  • On chip instruction and data SRAM configurable
  • Configurable I-Cache & D-Cache with ECC, 16-64KB
  • SMP supports up to 16 cores
AI
AR/VR
Storage
UX900 Core Machine/Supervisor/
User Mode
UX900 Core Machine/Supervisor/
User Mode
UX900 Core Machine/Supervisor/
User Mode
ILM
DLM
ICache w/ECC
DCache w/ECC
DSP/FPU/VPU
MMU
MMU
  • Series 64-Bit, in-order 9 stage Harvard Pipeline,Single-Issue or Dual-Issue
  • RISC-V RV32/64IMACFDPVBZfh ISA supported
  • On chip instruction and data SRAM configurable
  • Configurable I-Cache & D-Cache with ECC, 16-64KB
  • MMU support,Support both 32b & 64b Linux Kernel
  • SMP supports up to 16 cores
  • System level cache configurable, supporting cache consistency
64b Linux
Application Processor
ADAS+robotics
Download 900 Product Brief
900 Series Performance and Configurability
Comparisons to Cortex-M7、R5 Comparisons to Cortex-A5、A7 Comparisons to Cortex-M85、R82 Comparisons to Cortex-A53、A55
Nuclei CPU IP N900 U900 NX900 UX900
Dhrystone(DMIPS/MHz) 2.84/6.05(Legal/Best Effort) 3.09/7.7(Legal/Best Effort)
CoreMark(CoreMarks/MHz) 5.5
Pipeline Stages 9
Issue Width Single-Issue or Dual-Issue,Configurable
User Mode & PMP(MPU) Configurable Configurable Configurable Configurable
Hardware multiplier and divider Configurable Configurable Configurable Configurable
Single-Precision/Double-Precision FPU Configurable Configurable Configurable Configurable
Instruction-Cache Configurable Configurable Configurable Configurable
Data-Cache Configurable Configurable Configurable Configurable
Digital Signal Processing (DSP) Configurable Configurable Configurable Configurable
NICE Configurable Configurable Configurable Configurable
TEE Configurable Configurable Configurable Configurable
Vector Extension Configurable Configurable Configurable Configurable
Cluster Cache Configurable Configurable Configurable Configurable
MMU No Configurable No Configurable
Multi-Processors Configurable Configurable Configurable Configurable
Customize a 900 series processor
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